Semiconductor memory devices are used in a wide variety of applications. Such memory devices receive data for storage, in what is called a Write operation, and provide stored data to devices external to the memory, in what is called a Read operations. Typically, the memory device is accessed through a bus or multiple bus system by an external device or bus-master, such as a microprocessor, memory controller, or application specific integrated circuit (ASIC). The bus transfers address, data, and control signals between the memory device and the bus-master accessing the memory device.
Many of today's high speed memory devices, such as static random access memories (SRAMs), may operate at speeds greater than the capability of a bus-master accessing the SRAM. In a Read operation, for example, the SRAM may provide the data earlier than a time at which the bus-master is ready to retrieve such data. Bus contention may then result, in which data read from the SRAM is driven onto the bus while other data still resides on the bus. Consequently, two or more devices are sourcing/sinking relatively high currents for some conflicting period of time, thereby increasing risk of latchup effects, increasing system power consumption, increasing power and ground noise, and potentially resulting in erroneous data values.
To avoid such bus contention problems, designers of systems including high speed memories often insert idle time between successive data transfer operations, thereby reducing system speed to significantly less than optimal levels. Additionally, system designers often match speed specifications of various devices included within the system. As such, a system designer may not be able to use a readily available and inexpensive memory device in a system having other components too slow to match the speed of the memory device.